Interesting evening read analysing quality of the verification techniques used on the current project. The paper does discuss statistics over last few years with focus on the first time success. It turns out, that most projects requires respin (in case of ASIC) or new design release (in case of FPGA).
For me as an engineer, the paper does not provide much because it do not recommend any techniques. The figure 8 can be used to compare the several verification techniques but the I would need more detailed discussion to prefer one technique over other.
According to the Figure 8, the constrained random has lowest percentage of the first silicon success which is 60 percent. The figure 6 states, that from all projects, about 33 percent achieves the first silicon success. These two numbers presents gap about 30 percent large. After reading the paper I am unsure what is the origin of the gap. What other project uses for verification? How successful are project without verification at all?
The second conclusion from the paper is that the application of the approaches and techniques for the safety critical systems do not increase change of the first silicon success.
I believe that the paper can be the source of the interesting information for the discussion about verification with management. As it nicely demonstrates, that others are late as well and that the correct application of the verification techniques increases chance of the first silicon success. It would be nice to know, how the application of the verification methodologies affect the timeline of the project. I would expect that the correct application of the verification through all phases of all projects will increase re-usability of the components from previous projects and reduce debugging time since most of the bugs will be catch during the simulation in verification tools instead during the system level testing.
Link to the paper: http://s3.mentor.com/public_documents/whitepaper/resources/mentorpaper_102839.pdf
For me as an engineer, the paper does not provide much because it do not recommend any techniques. The figure 8 can be used to compare the several verification techniques but the I would need more detailed discussion to prefer one technique over other.
According to the Figure 8, the constrained random has lowest percentage of the first silicon success which is 60 percent. The figure 6 states, that from all projects, about 33 percent achieves the first silicon success. These two numbers presents gap about 30 percent large. After reading the paper I am unsure what is the origin of the gap. What other project uses for verification? How successful are project without verification at all?
The second conclusion from the paper is that the application of the approaches and techniques for the safety critical systems do not increase change of the first silicon success.
I believe that the paper can be the source of the interesting information for the discussion about verification with management. As it nicely demonstrates, that others are late as well and that the correct application of the verification techniques increases chance of the first silicon success. It would be nice to know, how the application of the verification methodologies affect the timeline of the project. I would expect that the correct application of the verification through all phases of all projects will increase re-usability of the components from previous projects and reduce debugging time since most of the bugs will be catch during the simulation in verification tools instead during the system level testing.
Link to the paper: http://s3.mentor.com/public_documents/whitepaper/resources/mentorpaper_102839.pdf
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